Method of forming an integrated circuit with two types of transistors
US7795096B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Dec 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.