Patent · US Active

Loop-back testing method and apparatus for IC

US7795895B2 · kind B2 · utility

3Cited by
1References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 28, 2007
Grant dateSep 14, 2010
Priority date
Expiry dateMay 28, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/31716
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A test system for testing operability of integrated circuits includes: a first IC, for modulating a first signal to generate a first modulated signal and transmitting the first modulated signal, and for receiving a second modulated signal and demodulating the second modulated signal to generate a second signal; a first loop antenna, coupled to the first IC, for receiving the first modulated signal and sending the first modulated signal back to the first IC as the second modulated signal; and a tester circuit coupled to the first IC, for generating the first signal to the first IC, receiving the second signal from the first IC, and comparing the first signal and the second signal to determine the operability of the first IC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.