Programmable latch based multiplier
US7795913B2 · kind B2 · utility
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78References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Jan 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1733
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.