Circuit design methodology to reduce leakage power

US7795914B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Tobias Gemmeke · Santa Clara, US
• Friedrich Schroeder · Stuttgart, DE
• Stefan Bonsels · Stuttgart, DE
• Dieter Wendel · Schenefeld, DE

Key dates

• Filing date: Oct 31, 2008
• Grant date: Sep 14, 2010
• Expiry date: Oct 31, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/0016
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value.