Semi-digital delay locked loop circuit and method
US7795937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2009 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Mar 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.