Manufacture of 3 dimensional MIM capacitors in the last metal level of an integrated circuit
US7796372B2 · kind B2 · utility
3Cited by
9References
21Claims
0Family size
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Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Mar 19, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12986
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is for fabricating an integrated circuit formed from a substrate and including several metallic interconnection levels in which, in a same plane parallel to the main plane of the substrate, is a plurality of thick horizontal metallic interconnection lines, as well as one or several MIM capacitors fitted with metallic electrodes that are orthogonal to the main plane of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.