State-retentive scan latch
US7796445B1 · kind B1 · utility
3Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Dec 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device can include 1) a sustained or constantly powered low leakage latch to and from which a volatile state is uploaded and downloaded, respectively, based on an active-to-low signal, and 2) an intermittently powered or de-powerable memory element, coupled to the low leakage latch, from which and to which the volatile state is uploaded and downloaded, respectively, based on the active-to-low signal and a de-powerable voltage across the de-powerable memory element is powered and un-powered, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.