Memory dies for flexible use and method for configuring memory dies
US7796446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Mar 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.