Computer hardware fault administration
US7796527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2006 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Jun 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.