Parallel architecture for matrix transposition
US7797362B2 · kind B2 · utility
7Cited by
6References
7Claims
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Key dates
| Filing date | Feb 23, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Jul 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30098
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.