Arithmetic processor, information processing apparatus and memory access method in arithmetic processor
US7797494B2 · kind B2 · utility
5Cited by
11References
10Claims
0Family size
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Key dates
| Filing date | Apr 3, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an information processing apparatus of this invention having a cache memory, a TLB and a TSB, a second retrieval unit retrieves a second physical address from an address translation buffer by using a second virtual address corresponding one-to-one to a first virtual address, and a prefetch controller enters a first address translation pair of the first virtual address from an address translation table into a cache memory by using a second physical address which is a result of the retrieval, thereby largely shortening the processing time of a memory access when a TLB miss occurs at the time of the memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.