Triple voting cell processors for single event upset protection
US7797575B2 · kind B2 · utility
17Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Feb 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system for operating three address concentrating processors, a common clock signal is transmitted to each of the three address concentrating processors. A common data unit is transmitted simultaneously to each of the three address concentrating processors. A received data unit is received simultaneously from each of the three address concentrating processors. Each of the received data units are compared to each other. An error correcting routine is activated when the data units received from the three address concentrating processors are not all identical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.