Multithreaded static timing analysis
US7797658B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Aug 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for executing multithreaded algorithm to provide static timing analysis of a chip design includes analyzing a chip design to identify various components and nodes associated with the components. A node tree is built with a plurality of nodes. The node tree identifies groups of nodes that are available in different levels. A size of node grouping for a current level is determined by looking up the node tree. Testing data for parallel processing of different size of node groupings using varied thread counts is compiled. An optimum thread count for the current level based on the size of node grouping in the node tree is identified from compiled testing data. Dynamic parallel processing of nodes in the current level is performed using the number of threads identified by the optimum thread count. An acceptable design of the chip is determined by the dynamic parallel processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.