Method of forming a MOSFET on a strained silicon layer
US7799648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2009 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jun 4, 2029 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC30B15/00
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.