Semiconductor integrated circuit
US7800140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | May 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.