Semiconductor integrated circuit and method of designing semiconductor integrated circuit
US7800151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jul 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
Abstract
In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.