Frequency adjustment for clock generator
US7800451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2008 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Sep 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional-N divider receives an input signal and supplies a divided signal divided in accordance with an integer divide control signal determined from a divide ratio. A phase interpolator is coupled to the fractional-N divider to adjust a phase of the divided signal according to a fractional portion of the divide ratio. The apparatus, responsive to a request for a frequency adjustment of the generated signal in a programmable number of steps, is configured to adjust the frequency of the generated signal from a beginning frequency to an ending frequency in the programmable number of steps by adjusting the supplied divide ratio at each step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.