Display panel driving circuit capable of minimizing circuit area by changing internal memory scheme in display panel and method using the same
US7800573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | May 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided is a display panel driving circuit. The display panel driving circuit rearranges and stores image data input of a predetermined number of source lines externally so that data of the same channel neighbor each other, and compares the rearranged data. If the rearranged data are identical, only one buffer is driven, and common data is transferred to a plurality of source lines, outputs the rearranged data according to each channel, sequentially outputs data according to each source line using source drivers of each channel. Thus, when output data neighboring source lines are identical, the current required for the buffer is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.