Patent · US Active

Latch-based random access memory

US7800936B2 · kind B2 · utility

1Cited by

5References

21Claims

0Family size

Assignee

LSI Logic Corporation · US

Inventors

Michael N. Dillon · Richfield, US
James Jensen · Tomball, US
Bret Alan Oeltjen · Apple Valley, US

Key dates

Filing date	Jul 7, 2008
Grant date	Sep 21, 2010
Priority date	—
Expiry date	Nov 20, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/413
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.