Patent · US Active

Digital data buffer with phase aligner

US7800975B2 · kind B2 · utility

5Cited by

1References

7Claims

0Family size

Assignee

TEXAS INSTRUMENTS DEUTSCHLAND GMBH · DE

Inventors

Gerd Rombach · Freising, DE
Soritios Tambouris · Munich, DE

Key dates

Filing date	Feb 8, 2008
Grant date	Sep 21, 2010
Priority date	—
Expiry date	Apr 30, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/0998
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A digital data buffer has at least one data path and a parallel reference data path. The data path includes a first and second data register, and the reference path includes a third data register. A learn cycle control signal is applied to a multiplexer for selecting between the data path and the reference data path and is also applied in parallel to control circuitry of a phase aligner. The learn cycle control signal is for adjusting the phase of a clock signal at a second clock output of a phase locked loop so as to optimize setup and/or hold timing at the data input of the second data register.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.