Interface system and methodology having scheduled connection responsive to common time reference
US7801132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2008 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/35
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An input interface system for mapping data packets, each comprising a header portion and a payload portion, from at least one source to at least one destination. An interface method and system between asynchronous data packet flows and synchronized switching systems, which utilize a global common time reference. The synchronized switching systems utilize a time frame switching method based on predefined switching schedules that are responsive to a global common time reference, where the global common time reference is divided into a plurality of contiguous periodic time frames. The asynchronous data packet flows are routed according to information contained in the packets' header. The interface method and system maps the header information of the asynchronous data packet flows to respective time frames that match the predefined switching schedule over the synchronized switching system. The interface system can aggregate multiple asynchronous data packet flows into a single pre-defined switching schedule over the synchronized switching system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.