Clock and data recovery circuits
US7801203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Mar 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/06
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data communication system comprising a first transmitter set configured to transmit a first output based on a first signal, the first output including one of a training pattern and a first data, the training pattern and the first data including clock information, a second transmitter set configured to transmit a second output based on the first signal, the second output including one of the training pattern and a second data, a first receiver set configured to generate a first received data based on the first output, a second receiver set configured to generate a second received data based on the second output, a clock and data recovery (CDR) circuit configured to extract the clock information based on the first signal and the first received data and provide a second signal indicating whether a frequency in-lock status is reached, a phase control circuit in the second receiver set, the phase control circuit being configured to detect a phase difference between the first received data and the second received data and provide a third signal indicating whether a phase in-lock status is reached, and a detector configured to generate the first signal based on the second signal and the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.