All digital phase locked loop architecture for low power cellular applications
US7801262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2006 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Apr 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.