Watermarking a chip design based on frequency of geometric structures
US7801325B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | May 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2201/0061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for watermarking a circuit design layout based on frequency or number of geometric structures. The method includes dividing a circuit design layout into a plurality of segments or tiles. Certain segments are selected, and within these selected segments, a router alters the number of geometric structures, such as vias and jogs, of the circuit design layout in the selected segments to form the watermark without relying on a netlist. The number of geometric structures is changed slightly so that a random sampling of segments would not identify the watermark since the variations would not be detectable or would be within acceptable variances, but the watermark would be readily identified if the selected segments are known. The watermark or portions thereof can be used to encode one or more data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.