Method for smart dummy insertion to reduce run time and dummy count
US7801717B2 · kind B2 · utility
2Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jan 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.