Systems and methods for code based error reduction
US7802163B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Apr 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various systems and methods for code based error reduction. For example, in one digital information system including a channel detector and a decoder, the channel detector receives an encoded data set and is operable to perform a column parity check. The channel detector provides an output representing the encoded data set. The decoder receives the output from the channel detector and is operable to perform two checks. The two checks may be one of: two pseudo-random parity checks, a pseudo-random parity check and a slope parity check, and two slope parity checks. In addition, the decoder provides another output representing the encoded data set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.