Area and power saving standard cell methodology
US7802216B2 · kind B2 · utility
4Cited by
1References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Feb 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.