Class scheduler for increasing the probability of processor access by time-sensitive processes
US7802256B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2005 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jul 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for enabling a general purpose operating system to maximize the probability of time-sensitive threads, e.g., multimedia threads, gaining access to CPU resources quickly enough to meet the demands of time-sensitive tasks while allowing time-insensitive threads to meet the demands of time-insensitive tasks, is disclosed. The priorities of time-sensitive threads in an operating system are adjusted so that the time-sensitive threads have a high probability of gaining access to CPU resources quickly enough to meet the demands of time-sensitive tasks while allowing time-insensitive threads to meet the demands of time-insensitive tasks. A system responsiveness cell (SRC) value is used to determine how quickly the operating system needs to respond to time-sensitive threads and time-insensitive threads. Priorities of threads are dynamically changed according to the relative CPU resource access requirements of system profile tasks. Criteria for mapping time-sensitive tasks are contained in system profile tasks. Priorities of cross-process groups of time-sensitive threads related to specific instances of tasks are adjusted according to the criteria in the system profile…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.