Source/emitter follower buffer driving a switching load and having improved linearity
US7804328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2008 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Jan 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/5031
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.