Caching in multicore and multiprocessor architectures
US7805575B1 · kind B1 · utility
105Cited by
15References
81Claims
0Family size
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Key dates
| Filing date | May 25, 2007 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Dec 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.