Managing memory access in a parallel processing environment
US7805577B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2006 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.