Memory addressing controlled by PTE fields
US7805587B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2006 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Sep 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention enable virtual-to-physical memory address translation using optimized bank and partition interleave patterns to improve memory bandwidth by distributing data accesses over multiple banks and multiple partitions. Each virtual page has a corresponding page table entry that specifies the physical address of the virtual page in linear physical address space. The page table entry also includes a data kind field that is used to guide and optimize the mapping process from the linear physical address space to the DRAM physical address space, which is used to directly access one or more DRAM. The DRAM physical address space includes a row, bank and column address. The data kind field is also used to optimize the starting partition number and partition interleave pattern that defines the organization of the selected physical page of memory within the DRAM memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.