Parallel link reset in link based system
US7805597B2 · kind B2 · utility
1Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | May 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A link based system including a plurality of processors is reset when transitioning from a slower speed to a higher speed mode during a booting process. One processor may coordinate the simultaneous establishment of link resetting of a plurality of other processors. In one embodiment, the processors may operate beginning with the farthest processor to reset their local links. Each processor sets its local links and if it determines, based on the speed of the link that the link has already been reset, it moves on to the next link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.