Shift-frequency scaling
US7805648B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 7, 2008 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
There is provided a method that includes, (a) determining a first clock frequency for shifting a first section of a scan pattern set through a path in a digital circuit such that a first power dissipated by the digital circuit while shifting the first section does not exceed a power limit, (b) determining a second clock frequency for shifting a second section of the scan pattern set through the path such that a second power dissipated by the digital circuit while shifting the second section does not exceed the power limit, (c) shifting the first section through the path at the first clock frequency, and (d) shifting the second section through the path at the second clock frequency, where first and second clock frequencies are different from one another. There is also provided a system that performs the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.