Low resistance gate for power MOSFET applications and method of manufacture

US7807536B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• Sreevatsa Sreekantham · West Jordan, US
• Ihsiu Ho · Salt Lake City, US
• Fred Session · Sandy, US
• Kent Naylor · Kaysville, US

Key dates

• Filing date: Aug 29, 2006
• Grant date: Oct 5, 2010
• Expiry date: Mar 20, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/685

Abstract

A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.