Standard cell without OD space effect in Y-direction
US7808051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.