Minimizing adverse effects of skew between two analog-to-digital converters
US7808408B2 · kind B2 · utility
18Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Feb 19, 2009 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Mar 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1205
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.