Sigma-delta modulator including truncation and applications thereof
US7808415B1 · kind B1 · utility
15Cited by
17References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 25, 2009 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | May 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/304
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.