System and method for monitoring negative bias in integrated circuits
US7808753B2 · kind B2 · utility
2Cited by
1References
14Claims
0Family size
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Key dates
| Filing date | Feb 27, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | May 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/0084
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A bias voltage monitoring circuit is disclosed which comprises a first device coupled between a positive high voltage power supply (VDD) and a first node, a second device coupled between the first node and a second node where the bias voltage is applied, and a pad coupled to the first node, wherein the first and second devices form a voltage divider and a voltage measured at the pad reflects the bias voltage, and the first device and the second device is so chosen that a voltage at the first node is always positive for a given range of the bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.