Power line layout
US7808804B2 · kind B2 · utility
12Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 9, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Sep 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines arranged perpendicular to the first power lines in the memory cell region to form a mesh arrangement of first and second power lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.