Memory repair circuit and repairable pseudo-dual port static random access memory
US7808847B2 · kind B2 · utility
8Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Apr 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/818
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory repair circuit and a repairable pseudo-dual port static random access memory (pseudo-dual port SRAM). The memory repair circuit uses fewer redundant column blocks and stores a few failed block addresses to reduce the required complexity of decoding the redundant column blocks. Thus, the present invention can reduce a layout area required by redundant memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.