Test circuit, system, and method for testing one or more circuit components arranged upon a common printed circuit board
US7809052B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 2006 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Jan 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.