Packet error signal generator
US7809066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2003 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Feb 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03382
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A software packet error system for a High Definition Television (HDTV) receiver. A data packet error signal is transferred from a forward error correcting Reed-Solomon decoder to a transport processor. In response to a segment sync signal, the transport processor generates an error signal which appears on a programmable output pin. The software packet error signal is synchronized with the outgoing data packet signal such that each data packet is bracketed or framed by its associating packet error signal. Precession of the start of the data packets forwarded on the transport but relative to the start of the data packets appearing at the output of the decoder occurs as a result of a training packet generated for every 312 data packets. The precession is reset at the beginning of every field and is predictable across the field duration with sufficient accuracy to make the software packet error mechanism feasible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.