High performance multilevel cache hierarchy
US7809889B2 · kind B2 · utility
4Cited by
3References
16Claims
0Family size
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Key dates
| Filing date | Jul 18, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Jan 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item misses in both the first cache level and in the second cache level, a line of data containing the requested data is obtained from a higher level of the hierarchical memory system. The line of data is allocated to both the first cache level and to the second cache level simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.