Low overhead access to shared on-chip hardware accelerator with memory-based interfaces
US7809895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Oct 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.