Error detector in a cache memory using configurable way redundancy
US7809980B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 6, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Jan 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.