Method for eliminating negative slack in a netlist via transformation and slack categorization
US7810062B2 · kind B2 · utility
5Cited by
10References
11Claims
0Family size
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Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Jan 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.