Thin film transistor array substrate
US7812352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2009 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Mar 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/40
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A TFT array substrate is disclosed. In the pixel structure of the TFT array substrate, patterned transparent conductive layers are disposed under a first metal layer (M1) and a second metal layer (M2) and most areas of the M1 and M2 are substituted by the patterned transparent conductive layers. So, the pixel structure has high aperture ratio and large storage capacitance. Besides, a scan bonding pad on the TFT array substrate includes a first patterned transparent conductive layer (T1), the M1 and a third patterned transparent conductive layer (T3). The M1 is disposed on the T1, and the T3 is electrically connected to the T1 via a contact hole in the M1. So, the contact resistance of the scan bonding pad is small. The data bonding pad on the TFT array substrate has similar design. Moreover, fabricating methods of TFT array substrates are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.