Semiconductor memory device with memory cells on multiple layers
US7812390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Sep 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.