Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers

US7812408B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Albert Ratnakumar · San Jose, US
• Peter J. McElheny · معلمی نژاد, US

Key dates

• Filing date: Oct 16, 2007
• Grant date: Oct 12, 2010
• Expiry date: Oct 16, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

An integrated circuit is provided with groups of transistors that handle different maximum voltage levels. The transistors may be metal-oxide-semiconductor transistors having body, source, drain, and gate terminals. The gate of each transistor may have a gate insulator and a gate conductor. The gate conductor may be formed from a semiconductor such as polysilicon. Adjacent to the gate insulator, the polysilicon gate conductor may have a depletion layer. The depletion layer may have a thickness that is related to the doping level in the polysilicon gate conductor. By reducing the doping level in the polysilicon gates of some of the transistors, the equivalent oxide thickness of those transistors is increased, thereby enhancing their ability to withstand elevated voltages without experiencing gate oxide breakdown due to hot carrier injection effects.